1. Field of the Invention
The present invention relates to a ferroelectric memory device comprising ferroelectric capacitors, and more specifically to a ferroelectric memory device which stores data of 3 or more values in one ferroelectric capacitor therein.
2. Description of the Related Art
Semiconductor memory devices are generally classified into volatile semiconductor memory devices such as DRAM (Dynamic Random Access Memory) which needs electric power to retain data written therein, and non-volatile semiconductor memory devices such as flash memories and EEPROM (Electric Erasable Programmable Read Only Memory) which do not need electric power to retain the written data. The performance of a semiconductor memory device is often expressed by a storage capacity, an access speed, and power consumption thereof.
As large-capacity, high-speed semiconductor memory devices, DRAMs are mainly used for the main storage of various kinds of computers. However, since DRAMs are volatile, a refresh operation is necessary in order to retain the written data, which leads to high power consumption.
Flash memories and EEPROMs are mainly used in file systems, memory cards, portable equipments and the like, as non-volatile semiconductor memory devices having large capacities and low power consumptions. However, flash memories and EEPROMs need a substantially long time to write data therein.
Meanwhile, ferroelectric memory devices comprising ferroelectric capacitors in memory cells thereof have been developed recently as semiconductor memory devices having advantages of both DRAMs and flash memories and EEPROMs.
A ferroelectric memory device can store binary data by using residual dielectric polarization which remains even when a voltage applied to a ferroelectric capacitor becomes 0.
FIG. 1 shows a configuration of a memory cell of a ferroelectric memory device of this kind.
In FIG. 1, a memory cell 1 comprises a ferroelectric capacitor 3 and a transistor 5 which is a transfer gate. The transistor 5 is formed by an NMOS (N-channel Metal Oxide Semiconductor).
A plate line PL is connected to a electrode 3a of the ferroelectric capacitor 3 for applying a voltage thereto. One transfer electrode 5a of the transistor 5 is connected to the other electrode 3b of the ferroelectric capacitor 3.
A bit line BL which is a transmission line of data is connected to the other transfer electrode 5b of the transistor 5. A word line WL which switches on and off the transistor 5 is connected to a gate electrode 5c of the transistor 5.
FIG. 2 shows a relation (hysteresis loop formed by "a", "b", "c", and "d") between a voltage E applied between the electrodes 3a and 3b of the ferroelectric capacitor 3 and a polarization charge density P thereof. The applied voltage E is a voltage VBL of the bit line BL relative to a reference voltage VPL of the plate line PL (that is, voltage VBL--voltage VPL).
Hereinafter, an operation of writing data in the memory cell 1 will be explained.
When data "1" are written in the memory cell 1 above, the plate line PL is set to 0V and the word line WL is set to high level, as shown in FIG. 3. In this state, the bit line BL is changed from 0V to VCC, then to 0V. 0V is a ground voltage, and VCC is a power supply voltage.
The high level voltage applied to the word line WL is set to a sum of VCC and a voltage higher than a threshold value of the transistor 5, and VCC applied to the bit line BL is transmitted to the electrode 3b of the ferroelectric capacitor 3 with certainty.
As a result, as shown in FIG. 4, a polarization charge of the ferroelectric capacitor 3 changes from "e" to "b", then to "c". Even in the case where the residual dielectric polarization value of the ferroelectric capacitor 3 before the write operation is not "e", the polarization charge always changes from "b" to "c", due to the write operation. As a result, the residual dielectric polarization value of the ferroelectric capacitor 3 after the operation of writing data "1" therein becomes a positive polarization charge value Pr ("c"). This is the state wherein data "1" are stored.
On the other hand, when data "0" are written in the memory cell 1, the plate line PL is set to VCC and the word line WL is set to at high level as shown in FIG. 5, and the bit line BL is changed from VCC to 0V, then from 0V to VCC.
As a result, as shown in FIG. 6, the polarization charge of the ferroelectric capacitor 3 changes from "f" to "a" via "d". Even in the case where the residual dielectric polarization value of the ferroelectric capacitor 3 before the write operation is not "f", the polarization charge always changes from "d" to "a", due to the write operation. As a result, the residual dielectric polarization value of the ferroelectric capacitor 3 after the operation of writing data "0" therein becomes a negative polarization charge value -Pr ("a"). This is the state wherein data "0" are stored.
FIG. 7 shows operation timings of the word line WL and the plate line PL and changes in the voltage of the bit line BL in an operation of reading data written in the memory cell 1. The read operation is performed by changing the voltage of the plate line PL form 0V to VCC then to 0V while the word line WL is at high level. The voltage of the bit line BL is set to 0V before the read operation, and in a floating state when the data are read.
FIG. 8 shows a change in the polarization charge of the ferroelectric capacitor 3 upon the read operation.
When data "1" are written in the memory cell 1, the polarization charge of the ferroelectric capacitor 3 changes from "c" to "d" by the read operation. An electric charge .DELTA.Q1 generated by the change in the polarization charge is distributed in a manner such that the voltages of the bit line BL and the electrode 3b of the ferroelectric capacitor 3 are equalized. As a result, as shown in FIG. 7, the voltage of the bit line BL rises to V1.
On the other hand, when data "0" are written in the memory cell 1, the polarization charge of the ferroelectric capacitor 3 changes from "a" to "d" by the read operation, as shown in FIG. 8. An electric charge .DELTA.Q2 generated by the change in the polarization charge is distributed in a manner such that the voltages of the bit line BL and of the electrode 3b of the ferroelectric capacitor 3 are equalized. As a result, as shown in FIG. 7, the voltage of the bit line BL rises to V0.
The voltage of the bit line BL is then changed from V1 to VCC, or from V0 to 0V by a sense amplifier which is not shown. The data "1" or "0" stored in the memory cell 1 are then read.
After completion of the reading, the polarization charge of the ferroelectric capacitor 3 changes to -Pr ("a") at the time the voltage of the plate line PL becomes 0V. For this reason, if the data written in the ferroelectric capacitor 3 are "1", the stored data are inverted, and rewriting is necessary.
Rewriting of data is performed when the voltage of the bit line BL is amplified by the sense amplifier. Upon the amplification, the voltage of the plate line PL is 0V. In the case where the read data are "1", the voltage of the bit line BL amplified by the sense amplifier becomes VCC, and the polarization charge of the ferroelectric capacitor 3 thus changes to "b", and the data "1" are written therein as in the case shown in FIG. 4.
If the read data are "0", the residual dielectric polarization charge of the ferroelectric capacitor 3 remains at "a" before and after the reading. The memory cell 1 remains in the state of storing data "0" therein.
The read and write operations of binary data "1" and "0" have been explained above. The value of the residual dielectric polarization of the ferroelectric capacitor 3 generally changes in response to the voltage of the bit line BL relative to the reference voltage of the plate line PL upon writing.
Therefore, as shown in FIG. 9, in the case where the residual dielectric polarization value of the ferroelectric capacitor 3 is "a" for example, the value changes to P1 when the bit line voltage (VBL-VPL) becomes V2.
Likewise, when the voltage of the bit line BL (VBL-VPL) becomes V3 in the case where the residual dielectric polarization value of the ferroelectric capacitor 3 is "a", the residual dielectric polarization value of the ferroelectric capacitor 3 becomes P2.
In other words, the state of the residual dielectric polarization of the ferroelectric capacitor 3 changes depending on the voltage applied to the bit line BL. Therefore, storing 3 or more values by using the residual dielectric polarization of the ferroelectric capacitor 3 is being discussed in various aspects.
However, in an attempt of realizing the ferroelectric memory device storing 3 or more values in the ferroelectric capacitor 3, the following problems, which do not occur in the case of storing binary data, occur.
The first problem is caused by the fact that the residual dielectric polarization of the ferroelectric capacitor 3 depends on not only the applied voltage but also the hysteresis.
For example, as shown in FIG. 10, a voltage V3 corresponding to a logical value is applied to the ferroelectric capacitor 3 and the logical value is written in the memory cell 1. After this write operation, the voltage V3 is applied to the ferroelectric capacitor 3 in order to write the logical value therein again.
On this occasion, the polarization charge of the ferroelectric capacitor 3 changes in a sequence of "a", "g", "h", "j" and "k". Therefore, even when the same voltage is applied to the ferroelectric capacitor 3 in order to write the same logical value, the residual dielectric polarization thereof changes to a plurality of values (P3 and P4 in this case). As a result, the written logical value is not restored properly.
The second problem is caused by disagreement between the polarization charge value upon applying a voltage to the bit line BL in a write operation and a residual dielectric polarization value after the write operation.
For example, in the hysteresis loop shown in FIG. 2, the polarization charge upon applying the voltage VCC to the bit line BL in the write operation changes to "b". Meanwhile, the residual dielectric polarization after the write operation changes to "c". Therefore, the residual dielectric polarization value is smaller than the polarization charge.
Consequently, whenever the data are read, the voltage of the bit line BL is smaller than the voltage thereof upon writing the data. Therefore, the data cannot be read properly by a simply comparing of the voltages upon reading and writing.
Furthermore, when data rewriting is necessary, if the voltage upon reading is simply used for the rewriting, a change to a residual dielectric polarization value different from the value before the rewriting is observed. In the case of binary data, the voltage upon reading can be amplified by a sense amplifier and no such problems occur.
The third problem is due to charging of a parasitic capacitor within the memory cell 1 upon writing data.
As shown in FIG. 11, a parasitic capacitor Cp exists between the electrode 3b of the ferroelectric capacitor 3 and the transfer gate 5a of the transistor 5 in the memory cell 1. The parasitic capacitor Cp is charged in response to the voltage applied to the bit line BL upon writing data.
Therefore, as shown in FIG. 12, the residual dielectric polarization immediately after completion of data writing is P5, which is a sum of a natural residual dielectric polarization Pr and the charge of the parasitic capacitor Cp. The electric charge in the parasitic capacitor Cp is discharged gradually with time, causing the residual dielectric polarization value P5 to change to Pr with time.
As a result, following elapsed time after the writing, data to be read changes. In the case of binary data, since data are read by the electric charges .DELTA.Q1 and .DELTA.Q2 shown in FIG. 8, the electric charge in the parasitic capacitor Cp can be treated as an error.
Due to the foregoing descriptions, there have been problems to be solved in order to store data of 3 or more values in the ferroelectric capacitor 3 and to read the stored data properly.